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ds07-12548-4e fujitsu semiconductor data sheet copyright?2002-2007 fujitsu limited all rights reserved 8-bit microcontroller cmos f 2 mc-8l mb89530 series mb89537/537c/538/538c/f538l/p538 mb89pv530 description the mb89530 series is a one-chip microcontroller featuring the f 2 mc-8l core supporting low-voltage and high- speed operation. built-in peripheral functions include timers, serial interface, a/d converter, and external interrupt. this product is an ideal general-purpose one-chip microcon troller for a wide variety of applications from household to industrial equipment, as well as use in portable devices. note : f 2 mc is the abbreviation of fuji tsu flexible microcontroller. features ? wide range of package options ? qfp package (1.00 mm pitch) ? two types of lqfp packages (0 .50 mm pitch, 0.65 mm pitch) ? sh-dip package ? bcc package (0.50 mm pitch) low voltage, high-speed operating capability ? minimum instruction execution time 0.32 s (at base oscillator 12.5 mhz) f 2 mc-8l cpu core ? instruction set optimized for controller operation ? multiplication/division instructions ? 16-bit calculation ? branching instructions with bit testing ? bit operation instructions, etc. (continued)
mb89530 series 2 (continued) ? five timer systems ? 8-bit pwm timer with 2 channels (usable as either interval timer of pwm timer) ? pulse width count timer (supports continuous meas urement or remote control receiving applications) ? 16-bit timer counter ? 21-bit time base timer ? watch prescaler (17-bit) uart ? synchronous or asynchronous operation, switchable 2 serial interfaces (serial i/o) ? selection of transfer direction (specify msb first or lsb first) for communication with a variety of devices 10-bit a/d converter (8 channels) ? external clock input for startup support (except for mb89f538l) ? time base timer output for startup support pulse generators (ppg) with 2-program capability ? 6-bit ppg with selection of pulse width and pulse period ? 12-bit ppg (2 channels) with sele ction of pulse width and pulse period i 2 c* interface circuits external interrupt 1 (single-clock : 4 channels, dual-clock : 3 channels) ? 4 or 3 independent inputs, release enabled from standby mode (include s edge detection function) external interrupt 2 (except for mb89 f538l : 8 channels, mb89f538l : 7 channels) ? 8 or 7 independent inputs, release enabled form standby mode (includes level edge detection function) standby modes (low po wer consumption modes) ? stop mode (oscillator stops, virtually no power consumed) ? sleep mode (cpu stops, power consumption reduced to one-third) ? sub clock mode ? watch mode watchdog timer reset i/o ports ? maximum port single-clock : except for mb89f538l : 53 mb89f538l : 52 dual-clock : except for mb89f538l : 51 mb89f538l : 50 ? 38 general-purpose i/o ports (cmos) (mb89f538l : 37) ? 2 general-purpose i/o ports (n-ch open drain) ? 8 general-purpose output ports (n-ch open drain) ? general-purpose input ports (cmos)single-clock system product : 5 dual-clock system product : 3 * : purchase of fujitsu i 2 c components conveys a lic ense under the philips i 2 c patent rights to use, these components in an i 2 c system provided that the system conforms to the i 2 c standard specification as defined by philips.
mb89530 series 3 product lineup (continued) part number parameter mb89537/537c mb89538/538c mb89 f538l mb89p538 mb89pv530 type mass produced (mask rom) product flash product one-time programmable product evaluation product rom capacity 32 k 8-bit (built-in rom) 48 k 8-bit (built-in rom) 48 k 8-bit (built-in flash memory) (write from general purpose eprom writer) 48 k 8-bit (built-in rom) (write from general purpose eprom writer) 48 k 8-bit (external rom) * 2 ram capacity 1 k 8-bit 2 k 8-bit operating voltage 2.2 v to 3.6 v* 1 (mb89537/538/537c/538c) 2.4 v to 3.6 v* 1 2.7 v to 5.5 v cpu functions basic instructions : 136 instruction bit length : 8 bits instruction length : 1 bit to 3 bits data bit length : 1, 8, 16 bits minimum instruction execution time : 0.32 s / 12.5 mhz minimum interrupt processing time : 2.88 s / 12.5 mhz ports input ports : single-clock 5 (4 also usable as external interrupts) dual-clock 3 (3 also usable as external interrupts) output-only ports (n-ch open drain) : 8 (8 also usable as adc input) i/o ports (n-ch open drain) : 2 (2 also usable as so2/sda or si2/scl) i/o ports (cmos) : 38 (21 have no other function) (except for mb89f538l) i/o ports (cmos) : 37 (21 have no other function) (mb89f538l) total (except for mb89f538l) : sing le-clock 53, 2system clock 51 total (mb89f538l) : single-cl ock 52, 2system clock 50 time base timer 21 bits interrupt periods at main clock oscillation frequency of 12.5mhz (approx. 0.655 ms, 2.621 ms, 20.97 ms, 335.5 ms) watchdog timer reset period of approx. 167.8 ms to 335. 6 ms at mail clock frequency of 12.5 mhz reset period of approx. 500 ms to 1000 ms at sub clock frequency of 32.768 khz. pwm timer 8-bit interval timer operation (supports square wave output, operating clock period : 1, 8, 16, 64 t inst * 3 ) pulse width measurement with 8-bit resolution (conversion period : 2 8 t inst * 3 to 2 8 64 t inst * 3 ) 2 channels (can also be used as interval time r, can also be used as ch.1 output and ch.2 count clock) watch prescaler interval times at 17-bit sub clock base frequency of 32.768 khz (approx. 31.25 ms, 0.25 s, 0.50 s, 1.00 s, 2.00 s, 4.00 s) peripheral functions
mb89530 series 4 (continued) *1 : depends on operating frequency. *2 : using external rom and mbm27c512. *3 : t inst represents instruction execution time. this can be selected as 1/4, 1/8, 1/16, 1/64 of the main clock cycle or 1/2 of the sub clock cycle. note : mb89537/538 have no built-in i 2 c functions. to use i 2 c functions, choose the mb 89pv530/p538/f538l/mb89537c/538c. part number parameter mb89537/537c mb89538/538c mb8 9f538l mb89p538 mb89pv530 pulse width count timer 8-bit one-shot timer operation (supports underflow output, oper ating clock period : 1, 4, 32 t inst * 3 , external) 8-bit reload timer operation (supports square wave output, opera ting clock period : 1, 4, 32 t inst * 3 , external) 8-bit pulse width measurement operation (continuous measurement, h width measuremen t, l width measurement, rise-to-rise, fall- to-fall, h width measurement and rise-to-rise) 16-bit timer/ counter 16-bit timer operation (operating clock period : 1 t inst * 3 , external) 16-bit event counter operation (sel ect rising, falling, or both edges) 16-bit 1 channel serial i/o 8 bits length, sele ction of lsb first or msb firs t, transfer clock (2, 8, 32 t inst * 3 , external) uart/sio clk synchronous/clk asynchronous data transfer capability (8, 9 bit with parity bit, or 7,8 bit without parity bit) . built-in baud rate generator provides selection of 14 baud rate settings. uart clk synchronous/clk asynchronous data transfer ca pability (4, 6, 7, 8 bit with parity bit, or 5, 7, 8, 9 bit without parity bit) . built-in baud rate generator provides selection of 14 baud rate settings. external clock output, 2-channel 8-bit pwm ti mer output also available for baud rate set- tings. external interrupt 1 single-clock : 4-channel independent, dual-clock : 3-channel independent selection of rising, falling, or both edge detection. can be used for recovery from standby mode (edge detection also available in stop mode) . external interrupt 2 except for mb89f538l : 8-channel independent l level detection, mb89f538l : 7-channel independent l level detection can be used for recovery from standby mode. 6-bit ppg, 12-bit ppg can generate square wave signals with programmable period. 6-bit 1 channel or 12-bit 2 channels. i 2 c bus interface 1-channel , compatible with intel system administrator bus version 1.0 and philips i 2 c specifications. 2-line communications (on mb89pv530/p538/f538l/537c/538c) a/d converter 10-bit resolution 8 channels. a/d conversion functions (conversion time : 60 t inst * 3 ) supports repeated calls from extern al clock (except for mb89f538l) supports repeated calls from internal clock. standard voltage input provided (avr) standby modes (power saving modes) sleep mode, stop mode, sub clock mode, watch mode. process cmos peripheral functions
mb89530 series 5 model differences and selection considerations o : model-package combination available x : model-package combination not available conversion sockets for pin pitch conversion (m anufactured by sunhayato corp.) can be used. contact : sunhayato corp. : tel : + 81-3-3984-7791 fax : + 81-3-3971-0535 url : http://www.advantest.co.jp/en-index.shtml package part number mb89537/537c mb89538/538c mb89 f538l mb89p538 mb89pv530 dip-64p-m01 o o o o x fpt-64p-m03 o o x x x fpt-64p-m06 o o o o x fpt-64p-m09 o o o o x lcc-64p-m19 o o o x x mdp-64c-p02 x x x x o mqp-64c-p01 x x x x o
mb89530 series 6 differences among products 1. memory capacity when this product is used in a evaluat ion product or other evaluation configur ation, it is necessary to carefully confirm the differences between the model being used and the product it is evaluating. particular attention should be given to the following (refer to " cpu core 1. memory space") . the program rom area starts from address 4000 h on the mb89p538, mb89f53 8l and mb89pv530 models. note upper limits on ram, such as stack areas, etc. 2. current consumption on the mb89pv530, the additional cu rrent consumed by the eprom is added at the connecting socket on the back side. when operating at low speed, the cu rrent consumption in the one-time pr om or eprom models is greater than on the mask rom models. however, current consumption in sleep or stop modes is identical. for details, refer to ? electrical characteristics?. 3. mask options the options available for use, and the method of specifying options, differ according to the model. before use, check the ? mask options? specification section. 4. wild register functions the following table shows areas in which wild register functions can be used. wild register usage areas part number address space mb89pv530 4000 h to ffff h mb89p538 4000 h to ffff h mb89f538l 4000 h to ffff h mb89537/537c 8000 h to ffff h mb89538/538c 4000 h to ffff h
mb89530 series 7 pin assignments (continued) (top view) (dip-64p-m01) (mdp-64c-p02) *1 : package top pin assignments (mb89pv530 only) nc : internal connection only. not for use. *2 : pin 10 is p47/int27/adst pins ex cept for mb89f538l and mod2 pin for mb89f538l. *3 : pin 25 and 26 are p63/int13, p64 pins for single-clock and x0a, x1a pins for dual-clock. *4 : the function of pin 57 depends on the model. for details, refer to ? pin descriptions? and ? handling devices?. pin no. pin name pin no. pin name pin no. pin name pin no. pin name 65a1573a181o689a8 66a1274a082o790a13 67 a7 75 o1 83 o8 91 a14 68 a6 76 o2 84 ce 92 v cc 69 a5 77 o3 85 a10 70 a4 78 v ss 86 oe 71 a3 79 o4 87 a11 72 a2 80 o5 88 a9 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 17 1 8 19 20 21 22 2 3 24 25 26 27 2 8 29 3 0 3 1 3 2 p 3 6/wto p 3 7/pto1 p40/int20/ec p41/int21/ s ck2 p42/int22/ s o2/ s da p4 3 /int2 3 / s i2/ s cl p44/int24/uck2 p45/int25/uo2 p46/int26/ui2 p47/int27/ad s t/mod2 * 2 p50/an0 p51/an1 p52/an2 p5 3 /an 3 p54/an4 p55/an5 p56/an6 p57/an7 av cc avr av ss p60/int10 p61/int11 p62/int12 p6 3 /int1 3 /x0a * 3 p64/x1a * 3 r s t mod0 mod1 x0 x1 v ss 64 6 3 62 61 60 59 5 8 57 56 55 54 5 3 52 51 50 49 4 8 47 46 45 44 4 3 42 41 40 3 9 38 3 7 3 6 3 5 3 4 33 v cc p 3 5/pwc p 3 4/pto2 p 33 / s i1 (ui1) p 3 2/ s o1 (uo1) p 3 1/ s ck1 (uck1) /lmco p 3 0/ppg0 3 /mco c/nc * 4 p00 p01 p02 p0 3 p04 p05 p06 p07 p10 p11 p12 p1 3 p14 p15 p16 p17 p20/pwck p21/ppg01 p22/ppg02 p2 3 p24 p25 p26 p27 92 91 90 8 9 88 8 7 8 6 8 5 8 4 83 8 2 8 1 8 0 79 65 66 67 6 8 69 70 71 72 7 3 74 75 76 77 7 8 v cc a14 a1 3 a 8 a9 a11 oe a10 ce o 8 o7 o6 o5 o4 a15 a12 a7 a6 a5 a4 a 3 a2 a1 a0 o1 o2 o 3 v ss * 1
mb89530 series 8 (continued) (top view) (fpt-64p-m03) (fpt-64p-m09) *1 : pin 2 is p47/int27/adst pins except for mb89f538l and mod2 pin for mb89f538l. *2 : pin 17 and 18 are p63/int13, p64 pins for single-clock and x0a, x1a pins for dual-clock. *3 : the function of pin 49 depends on the model. for details, refer to ? pin descriptions? and ? handling devices?. 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 p46/int26/ui2 p47/int27/ad s t/mod2 * 1 p50/an0 p51/an1 p52/an2 p5 3 /an 3 p54/an4 p55/an5 p56/an6 p57/an7 av cc avr av ss p60/int10 p61/int11 p62/int12 p00 p01 p02 p0 3 p04 p05 p06 p07 p10 p11 p12 p1 3 p14 p15 p16 p17 4 8 47 46 45 44 4 3 42 41 40 3 9 38 3 7 3 6 3 5 3 4 33 64 6 3 62 61 60 59 5 8 57 56 55 54 5 3 52 51 50 49 17 1 8 19 20 21 22 2 3 24 25 26 27 2 8 29 3 0 3 1 3 2 p6 3 /int1 3 /x0a * 2 p64/x1a * 2 r s t mod0 mod1 x0 x1 v ss p27 p26 p25 p24 p2 3 p22/ppg02 p21/ppg01 p20/pwck p45/int25/uo2 p44/int24/uck2 p4 3 /int2 3 / s i2/ s cl p42/int22/ s o2/ s da p41/int21/ s ck2 p40/int20/ec p 3 7/pto1 p 3 6/wto v cc p 3 5/pwc p 3 4/pto2 p 33 / s i1 (ui1) p 3 2/ s o1 (uo1) p 3 1/ s ck1 (uck1) /lmco p 3 0/ppg0 3 /mco c/nc * 3
mb89530 series 9 (continued) (top view) (fpt-64p-m06) (mqp-64c-p01) *1 : package top pin assignments (mb89pv530 only) nc : internal connection only. not for use. *2 : pin 3 is p47/int27/adst pins exce pt for mb89f538l and mo d2 pin for mb89f538l. *3 : pin 18 and 19 are p63/int13, p64 pins for single-clock and x0a, x1a pins for dual-clock. *4 : the function of pin 50 depends on the model. for details, refer to ? pin descriptions? and ? handling devices?. pin no. pin name pin no. pin name pin no. pin name pin no. pin name 65 nc 73 a2 81 nc 89 oe 66a1574a182o490nc 67a1275a083o591a11 68 a7 76 nc 84 o6 92 a9 69 a6 77 o1 85 o7 93 a8 70 a5 78 o2 86 o8 94 a13 71 a4 79 o3 87 ce 95 a14 72 a3 80 v ss 88 a10 96 v cc 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 17 1 8 19 p 3 0/ppg0 3 /mco c/nc * 4 p00 p01 p02 p0 3 p04 p05 p06 p07 p10 p11 p12 p1 3 p14 p15 p16 p17 p20/pwck 51 50 49 4 8 47 46 45 44 4 3 42 41 40 3 9 38 3 7 3 6 3 5 3 4 33 p45/int25/uo2 p46/int26/ui2 p47/int27/ad s t/mod2 * 2 p50/an0 p51/an1 p52/an2 p5 3 /an 3 p54/an4 p55/an5 p56/an6 p57/an7 av cc avr av ss p60/int10 p61/int11 p62/int12 p6 3 /int1 3 /x0a * 3 p64/x1a * 3 64 6 3 62 61 60 59 5 8 57 56 55 54 5 3 52 r s t mod0 mod1 x0 x1 v ss p27 p26 p25 p24 p2 3 p22/ppg02 p21/ppg01 94 95 96 65 66 67 6 8 8 4 83 8 2 8 1 8 0 79 7 8 20 21 22 2 3 24 25 26 27 2 8 29 3 0 3 1 3 2 p44/int24/uck2 p4 3 /int2 3 / s i2/ s cl p42/int22/ s o2/ s da p41/int21/ s ck2 p40/int20/ec p 3 7/pto1 p 3 6/wto v cc p 3 5/pwc p 3 4/pto2 p 33 / s i1 (ui1) p 3 2/ s o1/ (uo1) p 3 1/ s ck1 (uck1) /lmco 8 5 8 6 8 7 88 8 9 90 91 92 9 3 77 76 75 74 7 3 72 71 70 69 * 1
mb89530 series 10 (continued) (top view) (lcc-64p-m19) *1 : pin 2 is p47/int27/adst pins except for mb89f538l and mod2 pin for mb89f538l. *2 : pin 17 and 18 are p63/int13, p64 pins for single-clock and x0a, x1a pins for dual-clock. *3 : the function of pin 49 depends on the model. for details, refer to ? pin descriptions? and ? handling devices?. 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 p46/int26/ui2 p47/int27/ad s t/mod2 ? 1 p50/an0 p51/an1 p52/an2 p5 3 /an 3 p54/an4 p55/an5 p56/an6 p57/an7 av cc avr av ss p60/int10 p61/int11 p62/int12 p00 p01 p02 p0 3 p04 p05 p06 p07 p10 p11 p12 p1 3 p14 p15 p16 p17 4 8 47 46 45 44 4 3 42 41 40 3 9 38 3 7 3 6 3 5 3 4 33 64 6 3 62 61 60 59 5 8 57 56 55 54 5 3 52 51 50 49 17 1 8 19 20 21 22 2 3 24 25 26 27 2 8 29 3 0 3 1 3 2 p6 3 /int1 3 /x0a ? 2 p64/x1a ? 2 r s t mod0 mod1 x0 x1 v ss p27 p26 p25 p24 p2 3 p22/ppg02 p21/ppg01 p20/pwck p45/int25/uo2 p44/int24/uck2 p4 3 /int2 3 / s i2/ s cl p42/int22/ s o2/ s da p41/int21/ s ck2 p40/int20/ec p 3 7/pto1 p 3 6/wto v cc p 3 5/pwc p 3 4/pto2 p 33 / s i1 (ui1) p 3 2/ s o1 (uo1) p 3 1/ s ck1 (uck1) /lmco p 3 0/ppg0 3 /mco c/nc *3
mb89530 series 11 pin descriptions (continued) pin no. pin name i/o circuit type* 7 function sh-dip* 1 mdip* 2 qfp* 3 mqfp* 4 lqfp* 5 bcc* 6 30 23 22 x0 a connecting pins to crystal oscillator circuit or other oscillator circuit. the x0 pin can connect to an external clock. in that case, x1 is left open. 31 24 23 x1 28 21 20 mod0 b input pins for memory access mode setting. connect directly to vss. 29 22 21 mod1 27 20 19 rst c reset i/o pin. this pin has pull-up resistance with cmos i/o or hysteresis input. at an internal reset request, an ?l? signal is ou tput. an ?l? level input initializes the internal circuits. 56 to 49 49 to 42 48 to 41 p00 to p07 d general purpose i/o ports. 48 to 41 41 to 34 40 to 33 p10 to p17 d general purpose i/o ports. 40 33 32 p20/pwck e general purpose i/o port.resource i/o pin (hysteresis input).hysteresis input. this pin also functions as a pwc input. 39 32 31 p21/ ppg01 d general purpose i/o port.this pin also functions as the ppg01 output. 38 31 30 p22/ ppg02 d general purpose i/o port.this pin also functions as the ppg02 output. 37 30 29 p23 d general purpose i/o port. 36 29 28 p24 d general purpose i/o port. 35 28 27 p25 d general purpose i/o port. 34 27 26 p26 d general purpose i/o port. 33 26 25 p27 d general purpose i/o port. 58 51 50 p30/ ppg03/ mco d general purpose i/o port.this pin also functions as the ppg03 output. 59 52 51 p31/sck1 (uck1) / lmco e general purpose i/o port.resource i/o pin (hysteresis input).this pin also functions as the uart/sio clock input/output pin. 60 53 52 p32/so1 (uo1) d general purpose i/o port.this pin also functions as the uart/sio clock input/output pin. 61 54 53 p33/si1 (ui1) e general purpose i/o port.resource input/output pin (hysteresis input).this pin also functions as the uart/ sio serial data input pin. 62 55 54 p34/pto2 d general purpose i/o port.this pin also functions as the pwm time 2 output pin. 63 56 55 p35/pwc e general purpose i/o port.resource i/o pin (hysteresis input).this pin also functions as a pwc input.
mb89530 series 12 (continued) pin no. pin name i/o circuit type* 7 function sh-dip* 1 mdip* 2 qfp* 3 mqfp* 4 lqfp* 5 bcc* 6 1 58 57 p36/wto d general purpose i/o port.resource output.this pin also functions as the pwc output pin. 25958p37/pto1d general purpose i/o port.resource output.this pin also functions as the pwm timer 1 output pin. 36059 p40/int20/ ec e general purpose i/o port.resource i/o pin (hysteresis input).this pin also functions as an external interrupt input or 16-bit timer/counter input. 46160 p41/int21/ sck2 e general purpose i/o port.resource i/o pin (hysteresis input).this pin also functions as an external interrupt input or sio clock i/o pin. 56261 p42/int22/ so2/sda g n-ch open drain output. resource i/o pin (hysteresi s only for int22 input) . this pin also functions as an external interrupt input, sio serial data output, or i 2 c data line. 66362 p43/int23/ si2/scl g n-ch open drain output. resource i/o pin (hysteresi s only for int23 input) . this pin also functions as an external interrupt, sio serial data input, or i 2 c clock i/o pin. 76463 p44/int24/ uck2 e general purpose i/o port. resource i/o pin (hysteresis input) . this pin also functions as an external interrupt input or uart clock i/o pin. 8164 p45/int25/ uo2 e general purpose i/o port. resource i/o pin (hysteresis input) . this pin also functions as an external interrupt input or uart data output pin. 921 p46/int26/ ui2 e general purpose i/o port. resource i/o pin (hysteresis input) . this pin also functions as an external interrupt input or uart data input pin. 10 3 2 p47/int27/ adst e except for mb89f 538l general purpose i/o port. resource i/o pin (hysteresis input) . this pin also functions as an external interrupt input or a/d converter clock input pin. mod2 b mb89f 538l input pin for memory access mode setting. connect to v ss directly. 11 to 18 4 to 11 3 to 10 p50/an0 to p57/an7 h n-ch open drain output port. this pin also functions as an a/d converter analog input pin. 22 to 24 15 to 17 14 to 16 p60/int10 to p62/int12 i general purpose input port. resource input pin (hysteresis input) . this pin also functions as an external interrupt input pin.
mb89530 series 13 (continued) *1 : dip-64p-m01 *2 : mdp-64c-p02 *3 : fpt-64p-m06 *4 : mqp-64c-p01 *5 : fpt-64p-m03/m09 *6 : lcc-64p-m19 *7 : for i/o circuit type, refer to ? i/o circuit type? . pin no. pin name i/o circuit type* 7 function sh-dip* 1 mdip* 2 qfp* 3 mqfp* 4 lqfp* 5 bcc* 6 25 18 17 p63/int13 i single-clock general purpose input port. resource input pin (hysteresis input) . this pin also functions as an external interrupt. x0a a dual-clock connected pin for sub clock. 26 19 18 p64 j single-clock general purpose input port. x1a a dual-clock connected pin for sub clock. 64 57 56 v cc ? power supply pin. 32 25 24 v ss ? ground pin (gnd) . 19 12 11 av cc ? a/d converter power supply pin. 20 13 12 avr ? a/d converter reference voltage input pin. 21 14 13 av ss ? a/d converter power supply pin. used at the same voltage level as the vss supply. 57 50 49 c ? mb89p538 if ?available? is selected for the step-down circuit stabilization time, v cc is fixed. if ?unavailable? is selected for the step-down circuit stabilization time, v ss is fixed. mb89pv530 mb89f538l mb89537/537c mb89538/538c nc pin
mb89530 series 14 external eprom socket pin function descriptions (mb89pv530 only) *1 : mdp-64c-p02 *2 : mqp-64c-p01 *3 : for i/o circuit type, refer to ? i/o circuit type? . pin no. pin name i/o circuit type* 7 function mdip* 1 mqfp* 2 65 66 67 68 69 70 71 72 73 74 66 67 68 69 70 71 72 73 74 75 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 o address output pins. 75 76 77 77 78 79 o1 o2 o3 i data input pins. 78 80 v ss o power supply pin (gnd) . 79 80 81 82 83 82 83 84 85 86 o4 o5 o6 o7 o8 i data input pins. 84 87 ce o rom chip enable pin. outputs an ?h? level signal in standby mode. 85 88 a10 o address output pin. 86 89 oe o rom output enable pin. outputs ?l? at all times. 87 88 89 91 92 93 a11 a9 a8 o address output pins. 90 94 a13 o 91 95 a14 o 92 96 v cc o eprom power supply pin. ? 65 76 81 90 nc o internally connected. these pins always left open.
mb89530 series 15 i/o circuit types (continued) type circuit remarks a oscillator feedback resistance high speed side = approx. 1 m ? low speed side = approx. 10 m ? b hysteresis input pull-down resistance built-in to mb89537/537c, mb89538/538c c pull-up resistance approx. 50 k ? hysteresis input d cmos i/o software pull-up resistance can be used. approx. 50 k ? e cmos i/o software pull-up resistance can be used. approx. 50 k ? n-ch n-ch x1 (x1a) x0 (x0a) p-ch p-ch clock input standby control r mode input r p-ch n-ch reset output reset input p-ch p-ch n-ch r pull-up control resistor digital output digital output port input p-ch p-ch n-ch r pull-up control resistors port input resource input digital output digital output
mb89530 series 16 (continued) type circuit remarks g n-ch open drain output hysteresis input cmos input h n-ch open drain output analog input (a/d converter) i hysteresis input cmos input software pull-up resistance can be used. approx. 50 k ? j cmos input software pull-up resistance can be used. approx. 50 k ? n-ch resource input port input digital output n-ch p-ch analog input digital output p-ch r pull-up control resistors port resource p-ch r pull-up control resistors port
mb89530 series 17 handling devices 1. preventing latch-up care must be taken to ensure that maximum voltage ratings are not exceeded (to prevent latch-up) . when cmos integrated circuit devices are subjected to applied voltages higher than vcc at input and output pins (other than medium- and high-withstand voltage pins), or to voltages lower than v ss, as well as when voltages in excess of rated levels are applied between the vcc and vss pins, the phenomenon known as latch-up can occur. when a latch-up condition occurs, supply current c an increase dramatically and may destroy semiconductor elements. in using semiconductor devices, always take sufficient care to avoid exceeding maximum ratings. also when switching power on or off to analog system s, care must be taken that analog power supplies (av cc , avr) and analog input signals do not exceed the level of the digital power supply. 2. power supply voltage fluctuations keep supply voltage levels as stable as possible. even within the warranted operating range of the vcc supply voltage, sudden changes in supply voltage can cause abnormal operation. as a measure for stability, it is recommended that the vcc ripple fluctuation (peak to peak value) should be kept within 10% of the referenc e vcc value on commercial power supply (50 hz-60 hz), and instantaneous voltage fluctuations such as at powe r-on and shutdown should be kept within a transient variability limit of 0.1v/ms. 3. treatment of unused input pins if unused input pins are left open, abnormal operation may result. any unus ed input pins should be connected to pull-up or pull-down resistance. 4. treatment of nc pins any pins marked ?nc? (not c onnected) must be left open. 5. treatment of power supply pins on models with built-in a/d converter even when a/d converters are not in use, pins should be connected so that av cc = v cc , and av ss = avr = v ss . 6. precautions for use of external clock even when an external clock signal is used, an oscillator stabilization wait period is used after power-on reset, or escape from sub clock mode or stop mode. 7. execution of programs on ram debugging of programs executed on ram c annot be performed even when using the mb89pv530. 8. wild register functions wild registers cannot be debugged with the mb89pv530 and tools. to verify o perations, actual in-device testing on the mb89p538 or mb89f538l is advised.
mb89530 series 18 9. details on handling c terminal of mb89530 series the mb89530 series contains the following products. the regulator integrated model and the regulator-less model have different performance characteristics. although these product models have the same internal resources, the operation sequence after a power-on reset is different between the regulator integrated model and regulator-less model. the operation sequence after a power-on reset of each model is shown below. as above, the regulator integrated model starts the cp u behind the regulator-less model. this is because the regulator requires a settling time for normal operation. the mb89p538 offers a choice of regulator-integrated and regulator-less models selectable depending on the c-terminal treatment. use the ri ght one for your mask board. 10. note to noise in th e external reset pin (rst ) if the reset pulse applied to the external reset pin (rst ) does not meet the specific ations, it may cause malfunc- tions. use caution so that the reset pulse less than the s pecifications will not be fed to the external reset pin (rst ) . part no. operation voltage integrated model terminal type terminal treatments mb89pv530 2.7 v to 5.5 v not included nc terminal not required mb89p538 included c terminal fixed to v cc not included fixed to v ss mb89537/537c 2.2 v to 3.6 v nc terminal not required mb89538/538c mb89f538l 2.3 v to 3.6 v power supply (v cc ) cpu operation of regulator integrated model cpu operation of regulator-less model voltage step-down circuit stabilization time + oscillation stabilization time (2 19 /f ch ) + (2 18 /f ch ) oscillation stabiliza- tion time (2 18 /f ch ) cpu started on regulator-less model (reset vector) cpu started on regulator integrated model (reset vector) f ch : crystal oscillator frequency
mb89530 series 19 programming and erasing flash memory on the mb89f538l 1. flash memory the flash memory is located between 4000 h and ffff h in the cpu memory map and incorporates a flash memory interface circuit that allows read access and pr ogram access from the cpu to be performed in the same way as mask rom. programming and erasing flash memo ry is also performed via the flash memory interface circuit by executing instructions in the cpu. this enables the flash memory to be updated in place under the control of the cpu, providing an effici ent method of updating program and data. 2. flash memory features 48 k byte 8-bit configuration : (16 k + 8 k + 8 k + 16 k sectors) automatic programming algorithm (embedded algorithm* : equivalent to mbm29lv200) includes an erase pause and restart function data polling and toggle bit for detection of program/erase completion detection of program/erase completion via cpu interrupt compatible with jedec-standard commands sector erasing (sectors can be combined in any combination) no. of program/erase cycles : 10,000 (min) * : embedded algorithm is a trademark of advanced micro devices. 3. procedure for programming and erasing flash memory programming and reading flash memory cannot be perfor med at the same time. accordingly, to program or erase flash memory, the program must first be copied from flash memory to ram so that programming can be performed without program access from flash memory. 4. flash memory register flash control status register (fmcs) address initial value 007a h 000x00-0 b rdyint inte we rdy bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 r/w r r/w r/w r/w r/w r/w re- served re- served re- served
mb89530 series 20 5. sector configuration the table below shows the sector configuration of flash memory and lists the addresse s of each sector for both during cpu access a flash memory programming. sector configuration of flash memory * : the programmer address is the address to be used instead of the cpu address when programming data from a parallel flash memory programmer. use the programmer address on programming or erasing using a general- purpose parallel programmer. 6. rom programmer adaptor and recommended rom programmers * : for the version of the programmer , contact the flash support group, inc. enquiries sunhayato corp. : tel : +81-3-3984-7791 fax : +81-3-3971-0535 url : http://www.advantest.co.jp/en-index.shtml flash support group, inc. : fax : +81-53-428-8377 e-mail : support@j-fsg.co.jp flash memory cpu address programmer address* 16 k bytes ffff h to c000 h 1ffff h to 1c000 h 8 k bytes bfff h to a000 h 1bfff h to 1a000 h 8 k bytes 9fff h to 8000 h 19fff h to 18000 h 16 k bytes 7fff h to 4000 h 17fff h to 14000 h part number package adaptor part no. recommended programmer manufacturer and model sunhayato corp. flash support group, inc. mb89f538l-101pf mb89f538l-201pf fpt-64p-m06 flash-64qf-32dp-8lf af9708* af9709* mb89f538l-101pfm mb89f538l-201pfm fpt-64p-m09 flash-64qf2-32dp-8lf2 mb89f538l-101p-sh mb89f538l-201p-sh dip-64p-m01 flash-64sd-32dp-8lf mb89f538l-101pv4 mb89f538l-201pv4 lcc-64p-m19 flash-64bcc-32dp-8lf
mb89530 series 21 one-time writing specifications with prom and eprom microcontrollers the mb89p538 has a prom mode with functions equivalent to the mbm27c1001, allowing writing with a general purpose rom writer using a proprietary adapter. note, however, that the use of electronic signature mode is not supported. rom writer adapters with some rom writers, stability of writi ng performance is enhanced by placing an 0.1 f capacitor between the vcc and vss pins. the following table lis ts adapters for use with rom writers. rom writer adapters inquiries should be addressed to sunhayato corp. : tel : +81-3-3984-7791 fax : +81-3-3971-0535 url : http://www.advantest.co.jp/en-index.shtml * : version 3 or later should be used. memory map for eprom mode the following illustration shows a memory ma p for eprom mode. there are no prom options. part number package compatible adapter mb89p538-101pf mb89p538-201pf fpt-64p-m06 rom-64qf-32dp-8la2* MB89P538-101PFM mb89p538-201pfm fpt-64p-m09 rom-64qf2-32dp-8la mb89p538-101p-sh mb89p538-201p-sh dip-64p-m01 rom-64sd-32dp-8la2* 4000 h ffff h 1ffff h 0000 h 0000 h ram rom i/o 00 8 0 h 4000 h 0 88 0 h ffff h 0200 h 0100 h normal operating mode general purpose register prohibited eprom mode (corresponding addresses on eprom writer) program (eprom) prohibited prohibited
mb89530 series 22 recommended screening conditions before one-time writing of microcontroller programs to prom, high temperature aging is recommended as a screening process for chips before they are mounted. the following diagram shows the flow of the screening process. about writing yields the nature of chips before one-time writing of microcont roller programs to prom prevents the use of all-bit writing tests. therefore it is not possible to guarantee writing yields of 100% in some cases. program, verify high temperature aging + 150 c, 48h read mount
mb89530 series 23 eprom writing to piggy-back/evaluation chips this section describes methods of writin g to eprom on piggy-back/evaluation chips. ? eprom model mbm27c512-20tv writer adapter for writing to eprom using a rom writer, use one of the writer adapters shown below (manufactured by sunhayato corp.) . inquiries should be addressed to sunhayato corp. : tel : +81-3-3984-7791 fax : +81-3-3971-0535 e-mail : http://www.advantest.co.jp/en-index.shtml memory space piggy-back/evaluation memory map writing to eprom 1) set up the eprom writer for the mbm27c512. 2) load program data to the erpom writer, in the area 4000 h to ffff h . 3) use the eprom writer to write to the area 4000 h to ffff h . package adapter socket model lcc-32 (rectangular) rom-32lc-28dp-yg 4000 h ffff h 0000 h 0000 h ram prom 4 8 k b yte s eprom i/o 00 8 0 h 4000 h ffff h 0 88 0 h normal operating mode prohibited (corresponding address on rom writer) prohibited
mb89530 series 24 block diagram 4 p6 3 /int1 3 /x0a * 2 p64/x1a * 2 p60/int10 to p62/int12 x0 x1 r s t p 3 0/ppg0 3 /mco p 3 2/ s o1 (uo1) p 3 4/pto2 p 3 5/pwc p 3 6/wto p 3 7/pto1 p 33 / s i1 (ui1) p 3 1/ s ck1 (uck1) / lmco f 2 mc- 8 l cpu mod0, mod1, mod2 * 1 , v cc , v ss , c/nc pwc uart/ s io 8 8 p00 to p07 p10 to p17 p20/pwck p21/ppg01 p22/ppg02 p40/int20/ec p41/int21/ s ck2 p44/int24/uck2 p45/int25/uo2 p46/int26/ui2 p47/int27/ad s t * 1 p50/an0 to p57/an7 av cc avr av ss p4 3 /int2 3 / s i2/ s cl p42/int22/ s o2/ s da p2 3 to p27 8 8 s io uart i 2 c sub clock main clock low voltage oscillator circuit (32.786 khz) clock control watch prescaler external interrupt 1 (edge) cmos i/o port oscillator circuit clock controller reset circuit ( watchdog timer ) 21-bit time base timer 6-bit ppf03 8-bit pwm timer 2 8-bit pwm timer 1 cmos i/o port 1kb ram/2kb ram wild register 32kb rom/48kb rom other pins cmos i/o port cmos i/o port 12-bit ppg01 12-bit ppg02 cmos i/o port 16-bit timer/ counter 1 external interrupt 2 (level) n-ch i/o cmos i/o port n-ch output 10-bit a/d converter port 6 port 0 port 1 port 2 port 4 port 3 port 5 internal databus *1 : p47/int27/adst pins except for mb89f538l, mod2 pin for mb89f538l *2 : p63/int13, p64 pins for single- clock, x0a, x1a pins for dual-clock
mb89530 series 25 cpu core 1. memory space the mb89530 series has 64 kbytes of memory space, containing all i/o, data areas, and program areas. the i/o area is located at the lowest addresses, with th e data area placed immediately above. the data area can be partitioned into register areas, stack areas, or dire ct access areas depending on the application. the program area is located at the opposite end of memory, closest to the highest addresses, a nd the highest part of this area is assigned to the tables of interrupt and reset ve ctors and vector call instructions. the following diagram shows the structure of memory space in the mb89530 series. memory map 0000 h ram rom i/o 00 8 0 h 0c 8 0 h 04 8 0 h ffff h 0200 h 0100 h 0c91 h 8 000 h ffc0 h 0000 h ram mb 8 95 3 7/5 3 7c mb 8 9pv5 3 0 mb 8 9p5 38 /f5 38 l mb 8 95 38 /5 38 c rom i/o 00 8 0 h 0c 8 0 h 0 88 0 h ffff h 0200 h 0100 h 0c91 h 4000 h ffc0 h gener a l p u rpo s e regi s ter gener a l p u rpo s e regi s ter open wild register open vector tables* 2 open wild register open vector tables* 2 *1 : the external rom area is on the mbm89pv530 only. *2 : vector tables (reset, interrupt, vector call instructions) external rom* 1
mb89530 series 26 2. registers the f 2 mc-8l series has two types of registers, dedicated- use registers within the cpu, and general-purpose registers in memory. the dedicated-use registers are the following. in addition, the ps register can be divided so that the upper 8 bits are used as a register bank pointer (rp), and the lower 8 bits as a condition code register (ccr). (refer to the following illustration.) program counter (pc) : 16 bits length, show s the location where in structions are stored. accumulator (a) : 16 bits length, a temporary memory register for calculation operations. the lower byte is used for 8-bit data processing instructions. temporary accumulator (t) : 16 bits length, performs calculations with the accumulator. the lower byte is used for 8-bit data processing instructions. index register (ix) : 16 bits length , a register for index modification. extra pointer (ep) : 16 bits length, a pointer indicating memory addresses. stack pointer (sp) : 16 bits length, indicates stack areas. program status (ps) : 16 bits length, contains register pointer and condition code. pc a t ix ep sp ps 16 bits : program counter : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status fffd h initial value not fixed not fixed not fixed not fixed not fixed i-flag = 0, il1, 0 = 11 other bits not fixed program status register configuration p s rp ccr 15 b it 14 1 3 12 11 10 9 8 7654 3 21 0 rp h i il1 il0 n z v c open open open
mb89530 series 27 the rp register shows the address of the register bank currently being used, so that the rp value and the actual address are related by the conversion ru le shown in the following illustration. the ccr register has bits that show the content of re sults of calculations and transferred data, and bits that control cpu operation during interrupts. in addition, the following general purpose registers are available. general purpose registers: 8 bits length, used to contain data. the general purpose registers are 8-bit registers locat ed in memory. there are eight such registers per bank, and the mb89530 series have up to 32 banks for use. the ban k currently in use is indicated by the register bank pointer (rp). h-flag : set to ?1? if calculations result in carry or bo rrow operations from bit 3 to bit 4, otherwise set to ?0?. this flag is used for decimal correction instructions. i-flag : this flag is set to ?1? if interrupts are enabled, and ?0? if interrupts are prohibited. the default value at reset is ?0?. il1, 0 : indicates the level of th e currently permitted interrupts. only interrupt requests having a more powerful le vel than the value of thes e bits will be processed. il1 il0 interrupt level strength 00 1 strong weak 01 102 113 n-flag : set to ?1? if the highest bit is ?1? after a calculation, otherwise cleared to ?0?. z-flag : set to ?1? if a calculation re sult is ?0?, otherwise cleared to ?0?. v-flag : set to ?1? if a two?s complement overflow results during a calculation, otherwise cleared to ?0?. c-flag : set to ?1? if a calculation results in a carry or borrow operation from bit 7, otherwise cleared to ?0?. this is also the shift-out value in a shift instruction. general purpose register area re al address conversion principle "0" "0" "0" "0" "0" "0" "0" "1" r4 r 3 r2 r1 r0 b 2 b 1 b 0 a7 a6 a5 a4 a 3 a2 a1 a0 a15 a14 a1 3 a12 a11 a10 a9 a 8 address generated rp upper o peration code lower
mb89530 series 28 ? register bank configuration r0 r1 r2 r3 r4 r5 r6 r7 address at this location = 0100 h + 8 (rp) memory area 32 banks
mb89530 series 29 i/o map (continued) address register name register description write/read initial value 00 h pdr0 port 0 data register r/w xxxxxxxx b 01 h ddr0 port 0 direction register w 0 0 0 0 0 0 0 0 b 02 h pdr1 port 1 data register r/w xxxxxxxx b 03 h ddr1 port 1 direction register w 0 0 0 0 0 0 0 0 b 04 h to 06 h (reserved area) 07 h sycc system clock control register r/w x -1 mm1 0 0 b 08 h stbc standby control register r/w 0 0 0 1 0 - - - b 09 h wdtc watchdog control register r/w 0 - - - xxxx b 0a h tbtc time base timer control register r/w 0 0 - - - 0 0 0 b 0b h wpcr watch prescaler control register r/w 0 0 - - 0 0 0 0 b 0c h pdr2 port 2 data register r/w xxxxxxxx b 0d h ddr2 port 2 direction register r/w 0 0 0 0 0 0 0 0 b 0e h pdr3 port 3 data register r/w xxxxxxxx b 0f h ddr3 port 3 direction register r/w 0 0 0 0 0 0 0 0 b 10 h pdr4 port 4 data register r/w xxxx 1 1 xx b 11 h ddr4 port 4 direction register r/w 0 0 0 0 - - 0 0 b 12 h pdr5 port 5 data register r/w 1 1 1 1 1 1 1 1 b 13 h pdr6 port 6 data register r xxxxxxxx b 14 h to 21 h (reserved area) 22 h smc11 serial mode control register 1 (uart) r/w 0 0 0 0 0 0 0 0 b 23 h src1 serial route control register (uart) r/w - - 0 1 1 0 0 0 b 24 h ssd1 serial status and da ta register (uart) r/w 0 0 1 0 0 - 1x b 25 h sidr1/ sodr1 serial input/output data register (uart) r/w xxxxxxxx b 26 h smc12 serial mode control register 2 (uart) r/w - - 1 0 0 0 0 1 b 27 h cntr1 pwm control register 1 r/w 0 0 0 0 0 0 0 0 b 28 h cntr2 pwm control register 2 r/w 0 0 0 - 0 0 0 0 b 29 h cntr3 pwm control register 3 r/w - 0 0 0 - - - - b 2a h comr1 pwm compare register 1 w xxxxxxxx b 2b h comr2 pwm compare register 2 w xxxxxxxx b 2c h pcr1 pwc pulse width control register 1 r/w 0 0 0 - - 0 0 0 b 2d h pcr2 pwc pulse width control register 2 r/w 0 0 0 0 0 0 0 0 b 2e h rlbr pwc reload buffer register r/w xxxxxxxx b 2f h smc21 serial mode control register 1 (uart/sio) r/w 0 0 0 0 0 0 0 0 b 30 h smc22 serial mode control register 2 (uart/sio) r/w 0 0 0 0 0 0 0 0 b 31 h ssd2 serial status and data register (uart/sio) r/w 0 0 0 0 1 - - - b 32 h sidr2/ sodr2 serial data register (uart/sio) r/w xxxxxxxx b
mb89530 series 30 (continued) address register name register description write/read initial value 33 h src2 baud rate generator reload register r/w xxxxxxxx b 34 h adc1 a/d control register 1 r/w 0 0 0 0 0 0 - 0 b 35 h adc2 a/d control register 2 r/w - 0 0 0 0 0 0 1 b 36 h addl a/d data register low r/w xxxxxxxx b 37 h addh a/d data register high r/w - - - - - - 0 0 b 38 h ppgc2 ppg2 control register (12-bit ppg) r/w 0 0 0 0 0 0 0 0 b 39 h prl22 ppg2 reload register 2 (12-bit ppg) r/w 0x0 0 0 0 0 0 b 3a h prl21 ppg2 reload register 1 (12-bit ppg) r/w xx0 0 0 0 0 0 b 3b h prl23 ppg2 reload register 3 (12-bit ppg) r/w xx0 0 0 0 0 0 b 3c h tmcr 16-bit timer control register r/w - - 0 0 0 0 0 0 b 3d h tchr 16-bit timer counter register high r/w 0 0 0 0 0 0 0 0 b 3e h tclr 16-bit timer counter register low r/w 0 0 0 0 0 0 0 0 b 3f h eic1 external interrupt 1 control register 1 r/w 0 0 0 0 0 0 0 0 b 40 h eic2 external interrupt 1 control register 2 r/w 0 0 0 0 0 0 0 0 b 41 h to 48 h (reserved area) 49 h ddcr ddc select register r/w - - - - - - - 0 b 4a h to 4b h (reserved area) 4c h ppgc1 ppg1 control register (12-bit ppg) r/w 0 0 0 0 0 0 0 0 b 4d h prl12 ppg1 reload register 2 (12-bit ppg) r/w 0x0 0 0 0 0 0 b 4e h prl11 ppg1 reload register 1 (12-bit ppg) r/w xx0 0 0 0 0 0 b 4f h prl13 ppg1 reload register 3 (12-bit ppg) r/w xx0 0 0 0 0 0 b 50 h iacr i 2 c address control register r/w - - - - - 0 0 0 b 51 h ibsr i 2 c bus status register r 0 0 0 0 0 0 0 0 b 52 h ibcr i 2 c bus control register r/w 0 0 0 0 0 0 0 0 b 53 h iccr i 2 c clock control register r/w 0 0 0 xxxxx b 54 h iadr i 2 c address register r/w - xxxxxxx b 55 h idar i 2 c data register r/w xxxxxxxx b 56 h eie2 external interrupt 2 control register r/w 0 0 0 0 0 0 0 0 b 57 h eif2 external interrupt 2 flag register r/w - - - - - - - 0 b 58 h rcr1 6-bit ppg control register 1 r/w 0 0 0 0 0 0 0 0 b 59 h rcr2 6-bit ppg control register 2 r/w 0x0 0 0 0 0 0 b 5a h ckr clock output control register r/w - - - - - - 0 0 b 5b h to 6f h (reserved area) 70 h smr serial mode register (sio) r/w 0 0 0 0 0 0 0 0 b 71 h sdr serial data register (sio) r/w xxxxxxxx b 72 h purr0 port 0 pull-up resistance register r/w 1 1 1 1 1 1 1 1 b 73 h purr1 port 1 pull-up resistance register r/w 1 1 1 1 1 1 1 1 b 74 h purr2 port 2 pull-up resistance register r/w 1 1 1 1 1 1 1 1 b 75 h purr3 port 3 pull-up resistance register r/w 1 1 1 1 1 1 1 1 b
mb89530 series 31 (continued) description of write/read symbols : description of initial values : note : do not use reserved spaces. address register name register description write/read initial value 76 h purr4 port 4 pull-up resistance register r/w 1 1 1 1 - -1 1 b 77 h wren wild register enable register r/w - - 0 0 0 0 0 0 b 78 h wror wild register data test register r/w - - 0 0 0 0 0 0 b 79 h purr6 port 6 pull-up resistance register r/w - - - 1 1 1 1 1 b 7a h fmcs flash control status register r/w 000x00 - 0 b 7b h ilr1 interrupt level setting register 1 w 1 1 1 1 1 1 1 1 b 7c h ilr2 interrupt level setting register 2 w 1 1 1 1 1 1 1 1 b 7d h ilr3 interrupt level setting register 3 w 1 1 1 1 1 1 1 1 b 7e h ilr4 interrupt level setting register 4 w 1 1 1 1 1 1 1 1 b 7f h itr interrupt test register access prohibited xxxxxx0 0 b c80 h wrarh1 upper address setting register 1 r/w xxxxxxxx b c81 h wrarl1 lower address setting register 1 r/w xxxxxxxx b c82 h wrdr1 data setting register 1 r/w xxxxxxxx b c83 h wrarh2 upper address setting register 2 r/w xxxxxxxx b c84 h wrarl2 lower address setting register 2 r/w xxxxxxxx b c85 h wrdr2 data setting register 2 r/w xxxxxxxx b c86 h wrarh3 upper address setting register 3 r/w xxxxxxxx b c87 h wrarl3 lower address setting register 3 r/w xxxxxxxx b c88 h wrdr3 data setting register 3 r/w xxxxxxxx b c89 h wrarh4 upper address setting register 4 r/w xxxxxxxx b c8a h wrarl4 lower address setting register 4 r/w xxxxxxxx b c8b h wrdr4 data setting register 4 r/w xxxxxxxx b c8c h wrarh5 upper address setting register 5 r/w xxxxxxxx b c8d h wrarl5 lower address setting register 5 r/w xxxxxxxx b c8e h wrdr5 data setting register 5 r/w xxxxxxxx b c8f h wrarh6 upper address setting register 6 r/w xxxxxxxx b c90 h wrarl6 lower address setting register 6 r/w xxxxxxxx b c91 h wrdr6 data setting register 6 r/w xxxxxxxx b r/w : read/write enabled r : read only w : write only 0 : this bit initialized to ?0?. 1 : this bit initialized to ?1?. x : the initial value of this bit is not determined. m : the initial value of this bit is a mask option. - : this bit is not used.
mb89530 series 32 electrical characteristics 1. absolute maximum ratings (avss = vss = 0 v) *1 : the parameter is based on av ss = v ss = 0 v *2 : avcc and vcc are to be used at the same potential. avr should not exceed avcc + 0.3 v. (continued) parameter symbol rating unit remarks min max supply voltage* 1 v cc av cc v ss ? 0.3 v ss + 4.0 v mb89537/538 mb89537c/538c mb89f538l *2 avr v ss ? 0.3 v ss + 4.0 v v cc av cc v ss ? 0.3 v ss + 6.0 v mb89p538 mb89pv530 *2 avr v ss ? 0.3 v ss + 6.0 v input voltage* 1 v i v ss ? 0.3 v cc + 0.3 v other than p42, p43 v ss ? 0.3 v ss + 6.0 v only p42, p43 output voltage* 1 v o v ss ? 0.3 v cc + 0.3 v other than p42, p43 v ss ? 0.3 v ss + 6.0 v only p42, p43 maximum clamp current i clamp ? 2.0 + 2.0 ma *3 total maximum clamp current | i clamp | ? 20 ma *3 ?l? level maximum output current i ol ? 15 ma ?l? level average output current i olav ? 4ma average value (operating current operating duty) ?l? level maximum total output current i ol ? 100 ma ?l? level average total output current i olav ? 40 ma average value (operating current operating duty) ?h? level maximum output current i oh ?? 15 ma ?h? level average output current i ohav ?? 4ma average value (operating current operating duty) ?h? level maximum total output current i oh ?? 50 ma ?h? level average total output current i ohav ?? 20 ma average value (operating current operating duty) current consumption p d ? 300 mw operating temperature t a ? 40 + 85 c storage temperature tstg ? 55 + 150 c
mb89530 series 33 (continued) *3 : ? applicable to pins : p00 to p07, p1 0 to p17, p20 to p27, p30 to p37, p40, p41, p44 to p47, p50 to p57, p60 to p64 ? use within recommended operating conditions. ? use at dc voltage (current) . ? the + b signal should always be applied with a limiting resistance placed between the + b signal and the microcontroller. ? the value of the limiting resistance should be set so that when the + b signal is applied the input current to the microcontroller pin does not exceed rated values , either instantaneously or for prolonged periods. ? note that when the microcontroller drive current is low, such as in the power saving modes, the + b input potential may pass through the protective di ode and increase the potential at the v cc pin, and this may affect other devices. ? note that if a + b signal is input when the microcon troller current is off (not fixe d at 0 v) , the power supply is provided from the pins, so that incomplete operation may result. ? note that if the + b input is applied during power-on, the powe r supply is provided from the pins and the resulting supply voltage may not be suffic ient to operate the power-on result. ? care must be taken not to leave the + b input pin open. ? note that analog system input/outpu t pins other than the a/d input pins (lcd drive pins, comparator input pins, etc.) cannot accept + b signal input. ? sample recommended circuits : warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. p-ch n-ch v cc r ? input/output equivalent circuits + b input (0 v to 16 v) limiting resistance protective diode
mb89530 series 34 2. recommended operating conditions (avss = vss = 0 v) * : varies according to frequen cy used, and instruction cycle. refer to ? ? operating voltage vs. operating freque ncy (mb89537/mb89538/mb89537c/mb89538c) ?, ? ? operating voltage vs. operating fr equency (mb89p538/mb89pv530) ? and ?5. a/d converter electrical characteristics?. ? operating voltage vs. operating freq uency (mb89537/mb89538/mb89537c/mb89538c) parameter symbol value unit remarks min max supply voltage v cc , av cc 2.2* 3.6 v range warranted for normal operation mb89537/538 mb89537c/538c 1.5 3.6 v ram status in stop mode 2.4 3.6 v range warranted for normal operation mb89f538l 1.5 3.6 v ram status in stop mode 2.7* 5.5 v range warranted for normal operation mb89p538 mb89pv530 1.5 5.5 v ram status in stop mode avr 2.4 av cc v operating temperature t a ? 40 + 85 c 4.0 3.6 3.0 2.4 2.2 2.0 1.0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 12.5 4.0 2.0 0.8 0.4 0.32 range of warranted analog precision : v cc = av cc = 2.4 v to 3.6 v operating voltage v cc (v) operating frequency (mhz) (at instruction cycle = 4 / f ch ) minimum instruction execution ti me (instruction cycles) ( s)
mb89530 series 35 ? operating voltage vs. operating frequency (mb89f538l) 4.0 3.6 3.0 2.4 2.0 1.0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 12.5 4.0 2.0 0.8 0.4 0.32 range of warranted analog precision : v cc = av cc = 2.4 v to 3.6 v operating voltage v cc (v) operating frequency (mhz) (at instruction cycle = 4 / f ch ) minimum instruction execution ti me (instruction cycles) ( s)
mb89530 series 36 ? operating voltage vs. operating frequency (mb89p538/mb89pv530) warning: the recommended operating conditions are requir ed in order to ensure the normal operation of the semiconductor device. all of the device?s electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. 5.5 5.0 4.0 3.5 3.0 2.0 2.2 2.7 1.0 0 1.0 4.0 2.0 2.0 3.0 4.0 5.0 0.8 6.0 7.0 8.0 9.0 10.0 0.4 11.0 12.0 12.5 0.32 range of warranted analog precision : v cc = av cc = 3.5 v to 5.5 v operating voltage v cc (v) operating frequency (mhz) (at instruction cycle = 4 / f ch ) minimum instruction execution time (instruction cycles) ( s) indicates warranted operation at t a = ? 10 c to + 55 c
mb89530 series 37 3. dc characteristics (av cc = v cc = 3.0 v, avss = vss = 0 v, t a = ? 40 c to + 85 c) (continued) parameter symbol pin name condition value unit remarks min typ max ?h? level input voltage v ih p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p60 to p64, si1, si2 ? 0.7 v cc ? v cc + 0.3 v v ihs rst , mod0, mod1, int20 to int27, uck1, ui1, int10 to int13, sck1, ec, pwck, pwc, sck2, uck2, ui2, adst ? 0.8 v cc ? v cc + 0.3 v v ihsmb scl, sda ? v ss + 1.4 ? v ss + 5.5 v with smb input buffer selected* v ihi2c ? 0.7 v cc ? v ss + 5.5 v with i 2 c input buffer selected* ?l? level input voltage v il p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p60 to p64, si1, si2 ? v ss ? 0.3 ? 0.3 v cc v v ils rst , mod0, mod1, int20 to int27, uck1, ui1, int10 to int13, sck1, ec, pwck, pwc, sck2, uck2, ui2, adst ? v ss ? 0.3 ? 0.2 v cc v v ilsmb scl, sda ? v ss ? 0.3 ? v ss + 0.6 v with smb input buffer selected* v ili2c ? v ss ? 0.3 ? 0.3 v cc v with i 2 c input buffer selected* open drain output applied voltage v d1 p50 to p57 ? v ss ? 0.3 ? v cc + 0.3 v v d2 p42, p43 v ss + 5.5 v ?h? level output voltage v oh p00 to p07, p10 to p17, p20 to p24, p30 to p37, p40, p41, p44 to p47 i oh = ? 2.0 ma 2.4 ?? v p25 to p27 i oh = ? 3.0 ma ?l? level output voltage v ol p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, rst i ol = 4.0 ma ?? 0.4 v input leak current (hi-z output leak current) i li p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p60 to p64 0.0 v < v i < v cc ? 5 ?+ 5 a with no pull-up resistance specified
mb89530 series 38 (continued) (av cc = v cc = 3.0 v, avss = vss = 0 v, t a = ? 40 c to + 85 c) * : the mb89pv530/p538/f538l/5 37c/538c have a built-in i 2 c function, and a choice of input buffers by software setting. the mb89537/538 have no built-in i 2 c functions, and therefore this standard does not apply. parameter symbol pin name condition value unit remarks min typ max open drain output leak current i liod p42, p43 0.0 v < v i < v ss + 5.5 v ?? 5 a pull-up resistance r pull p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40, p41, p44 to p47, p60 to p64, rst v i = 0.0 v 25 50 100 k ? with pull-up resistance is selected. the rst signal is excluded. supply current i cc1 v cc f ch = 10.0 mhz t inst = 0.4 s ? 6 10 ma normal operation ?? 45 ma flash memory programming/erase mb89f538l i cc2 f ch = 10.0 mhz t inst = 6.4 s ? 1.5 3 ma i ccs1 f ch = 10.0 mhz t inst = 0.4 s ? 2 4 ma sleep mode i ccs2 f ch = 10.0 mhz t inst = 6.4 s ? 1 2 ma sleep mode i ccl f cl = 32.768 khz ? 13ma sub mode mb89p538/pv530 f cl = 32.768 khz t a = + 25 c ? 35 90 a sub mode mb89f538l f cl = 32.768 khz ? 20 50 a sub mode mb89537/538 mb89537c/538c i ccls f cl = 32.768 khz ? 15 30 a sub, sleep modes except mb89f538l f cl = 32.768 khz t a = + 25 c ? 15 30 a watch mode, main stop mb89f538l i cct f cl = 32.768 khz ? 515 a watch mode, main stop except mb89f538l f cl = 32.768 khz t a = + 25 c ? 515 a sub, sleep modes mb89f538l i cch t a = + 25 c ? 15 a sub, stop modes i a av cc f ch = 10.0 mhz ? 13ma a/d conversion running i ah t a = + 25 c ? 15 a a/d stopped input capacitance c in except v cc , v ss , av cc , av ss f = 1 mhz ? 515pf
mb89530 series 39 4. ac characteristics (1) reset timing (v cc = 3.0 v, avss = vss = 0 v, t a = ? 40 c to + 85 c) notes : ? t hcyl is the main clock oscillator period. ? if the reset pulse applied to the external reset pin (rst ) does not meet the specifications, it may cause malfunctions. use caution so that the reset pulse less t han the specifications will not be fed to the external reset pin (rst ) . (2) power-on reset (avss = vss = 0 v, t a = ? 40 c to + 85 c) note : be sure that the power supply will come on within the selected os cillator stabilization period. also, when varying the supply voltage during operation, it is re commended that the supply voltage be increased gradually. parameter symbol condition value unit min max rst ?l? pulse width t zlzh ? 48 t hcyl ? ns parameter symbol condition value unit remarks min max power on time t r ? 0.5 50 ms power shutoff time t off ? 1 ? ms waiting time until power-on rst 0.2 v cc 0.2 v cc t zlzh v cc t r 2.2 v 0.2 v 0.2 v 0.2 v t off
mb89530 series 40 (3) clock timing standards (avss = vss = 0 v, t a = ? 40 c to + 85 c) parameter symbol pin name condition value unit remarks min typ max clock frequency f ch x0, x1 ? 1 ? 12.5 mhz main clock f cl x0a, x1a ? 32.768 ? khz sub clock clock cycle time t hcyl x0, x1 80 ? 1000 ns main clock t lcyl x0a, x1a ? 30.5 ? s sub clock input clock pulse width p wh p wl x0 20 ?? ns external clock p whl p wll x0a ? 15.2 ? s external clock input clock rise, fall time t cr t cf x0 ?? 10 ns external clock x0, x1 timing and application conditions clock application conditions t hcyl p wh t cr t cf p wl 0.2 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc x0 x0 x1 c 1 c 2 f ch f ch x0 x1 using a crystal oscillator or ceramic oscillator using an external clock signal open
mb89530 series 41 (4) instruction cycle (avss = vss = 0 v, t a = ? 40 c to + 85 c) parameter symbol rated value unit remarks instruction cycle (minimum instruction execution time) t inst 4/f ch , 8/f ch , 16/f ch , 64/f ch s operating at f ch = 12.5 mhz (4/f ch ) t inst = 0.32 s 2/f cl s operating at f cl = 32.768 khz t inst = 61.036 s x0a, x1a timing and application conditions clock application conditions t lcyl p whl t cr t cf p wll 0.2 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc x0a x0a x1a x0a x1a c 1 c 2 f cl r d f cl using a crystal oscillator or ceramic oscillator using an external clock signal open
mb89530 series 42 (5) serial i/o timing (v cc = 3.0 v, avss = vss = 0 v, t a = ? 40 c to + 85 c) note : for t inst refer to ? (4) instruction cycle?. parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck, uck internal clock operation 2 t inst ? s sck so t slov sck, so, uck, uo ? 200 + 200 ns valid si sck t ivsh si, sck, ui, uck 200 ? ns sck valid si hold time t shix sck, si, uck, ui 200 ? ns serial clock ?h? pulse width t shsl sck, uck external clock operation 1 t inst ? s serial clock ?l? pulse width t slsh 1 t inst ? s sck so time t slov sck, so, uck, uo 0 200 ns valid si sck t ivsh si, sck, ui, uck 200 ? ns sck valid si hold time t shix sck, si, uck, ui 200 ? ns internal shift clock mode external shift clock mode s ck uck s o uo s i ui t s cyc t iv s h t s lov t s hix 0. 8 v 0. 8 v 2.4 v 0. 8 v cc 0.2 v cc 0. 8 v cc 0.2 v cc 0. 8 v 2.4 v s ck uck s o uo s i ui t s l s h t s h s l t iv s h t s lov t s hix 0.2 v cc 0. 8 v 2.4 v 0. 8 v cc 0.2 v cc 0. 8 v cc 0.2 v cc 0.2 v cc 0. 8 v cc 0. 8 v cc
mb89530 series 43 (6) peripheral input timing (v cc = 3.0 v, avss = vss = 0 v, t a = ? 40 c to + 85 c) note : for t inst refer to ? (4) instruction cycle?. parameter symbol pin name condition value unit min max peripheral input ?h? level pulse width 1 t ilih1 int10 to int13, int20 to int27, ec, pwc, pwck ? 2 t inst ? s peripheral input ?l? level pulse width 1 t ihil1 ? 2 t inst ? s peripheral input ?h? level pulse width 2 t ilih2 adst ? 2 8 t inst ? s peripheral input ?l? level pulse width 2 t ihil2 ? 2 8 t inst ? s ec, int, pwc, pwck t ihil1 t ilih1 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc adst t ihil2 t ilih2 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc
mb89530 series 44 (7) i 2 c timing (v cc = 3.0 v, avss = vss = 0 v, t a = ? 40 c to + 85 c) notes : ? for t inst refer to ? (4) instruction cycle?. ? the value ?m? in the above table is the value from the shift clock frequency setting bits (cs4-cs3) in the i 2 c clock control register ?iccr?. for details, refer to the register description in the hardware manual. ? the value ?n? in the above table is the value from the shift clock frequency setting bits (cs2-cs0) in the i 2 c clock control register ?iccr?. for details, refer to the register description in the hardware manual. ? t dosu appears when the interrupt period is longer than the scl ?l? width. ? the rated values for sda and scl assume a start up time of 0 ns. parameter symbol pin name condition value unit remarks min max start condition output t sta scl sda ? 1 / 4 t inst m n ? 20 1 / 4 t inst m n + 20 ns master only stop condition output t sto scl sda ? 1 / 4 t inst (m n + 8) ? 20 1 / 4 t inst (m n + 8) + 20 ns master only start condition detection t sta scl sda ? 1 / 4 t inst 6 + 40 ? ns stop condition detection t sto scl sda ? 1 / 4 t inst 6 + 40 ? ns restart condition output t stasu scl sda ? 1 / 4 t inst (m n + 8) ? 20 1 / 4 t inst (m n + 8) + 20 ns master only restart condition detection t stasu scl sda ? 1 / 4 t inst 4 + 40 ? ns scl output ?l? width t low scl ? 1 / 4 t inst m n ? 20 1 / 4 t inst m n + 20 ns master only scl output ?h? width t high scl ? 1 / 4 t inst (m n + 8) ? 20 1 / 4 t inst (m n + 8) + 20 ns master only sda output delay time t do sda ? 1 / 4 t inst 4 ? 20 1 / 4 t inst 4 + 20 ns setup after sda output interrupt interval t dosu sda ? 1 / 4 t inst 4 ? 20 ? ns scl input ?l? width t low scl ? 1 / 4 t inst 6 + 40 ? ns scl input ?h? width t high scl ? 1 / 4 t inst 2 + 40 ? ns sda input setup t su sda ? 40 ? ns sda input hold t ho sda ? 0 ? ns
mb89530 series 45 ? i 2 c interface [data sending (master/slave) ] ? i 2 c interface [data sending (master/slave) ] 9 ack t do t su t su t dosu t do t ho t low t sta t stasu sda scl 1 sda scl 67 8 9 t su t high t low t ho t do t do t dosu t sto ack
mb89530 series 46 5. a/d converter electrical characteristics (1) mb89537/538/537c/538c (v cc = 2.4 v to 3.6 v, av ss = v ss = 0 v, t a = ? 40 c to + 85 c) * : includes sampling time (2) mb89f538l (v cc = 2.4 v to 3.6 v, av ss = v ss = 0 v, t a = ? 40 c to + 85 c) * : includes sampling time parameter symbol pin name condition value unit remarks min typ max resolution capability ? ? ??? 10 bit av cc = v cc total error avr = av cc ?? 3.0 lsb linear error ?? 2.5 lsb differential linear error ?? 1.9 lsb zero transition voltage v ot av ss ? 1.5 lsb av ss + 0.5 lsb av ss + 2.5 lsb mv full scale transition voltage v fst avr ? 3.5 lsb avr ? 1.5 lsb avr + 1.5 lsb mv inter-channel variation ? ?? 4.0 lsb conversion time ? ? 60 t inst ? s* sampling time ? 16 t inst ? s analog input current i ain an0 to an7 ?? 10 a analog input voltage v ain av ss ? avr v reference voltage ? avr av ss + ? av cc v reference voltage supply current i r a/d running ? 200 ? a i rh a/d off ?? 5 a parameter symbol pin name condition value unit remarks min typ max resolution capability ? ? ??? 10 bit av cc = v cc total error avr = av cc ?? 3.0 lsb linear error ?? 2.5 lsb differential linear error ?? 1.9 lsb zero transition voltage v ot av ss ? 1.5 lsb av ss + 0.5 lsb av ss + 2.5 lsb mv full scale transition voltage v fst avr ? 3.5 lsb avr ? 1.5 lsb avr + 1.5 lsb mv inter-channel variation ? ?? 4.0 lsb conversion time ? ? 60 t inst ? s* sampling time ? 16 t inst ? s analog input current i ain an0 to an7 ?? 10 a analog input voltage v ain 0 ? avr v reference voltage ? avr av ss + ? av cc v reference voltage supply current i r a/d running ? 200 ? a i rh a/d off ?? 5 a
mb89530 series 47 (3) mb89p538/pv530 (v cc = 2.4 v to 3.6 v, av ss = v ss = 0 v, t a = ? 40 c to + 85 c) * : includes sampling time parameter symbol pin name condition value unit remarks min typ max resolution capability ? ? ??? 10 bit av cc = v cc total error avr = av cc ?? 3.0 lsb linear error ?? 2.5 lsb differential linear error ?? 1.9 lsb zero transition voltage v ot av ss ? 1.5 lsb av ss + 0.5 lsb av ss + 2.5 lsb mv full scale transition voltage v fst avr ? 3.5 lsb avr ? 1.5 lsb avr + 1.5 lsb mv inter-channel variation ? ?? 4.0 lsb conversion time ? ? 60 t inst ? s* sampling time ? 16 t inst ? s analog input current i ain an0 to an7 ?? 10 a analog input voltage v ain 0 ? avr v reference voltage ? avr av ss + ? av cc v reference voltage supply current i r a/d running ? 400 ? a i rh a/d off ?? 5 a
mb89530 series 48 (4) a/d converter terms and definitions resolution the level of analog variation that ca n be distinguished by the a/d converter. linear error (unit : lsb) the deviation between the value along a strai ght line connecting the zero transition point (?00 0000 0000? ?00 0000 0001?) of a device and the full-scale transition point (?11 1111 1110? ?11 1111 1111?) , compared with the actual conversion values obtained. differential linear error (unit : lsb) the deviation from the theoretical input voltage requ ired to produce a change of 1 lsb in output code. total error (unit : lsb) the difference between theoretical conver sion value and actual conversion value. (continued) v fst 1.5 lsb 1 lsb 0.5 lsb v ot avr av ss 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h v nt (1 lsb i n + 0.5 lsb) avr av ss 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h theoretical input/output characteristics analog input digital output 1 lsb = v fst ? v ot 1022 (v) total error analog input digital output total error in digital output n = v nt ? {1 lsb n + 0.5 lsb} 1 lsb actual conversion characteristics actual conversion characteristics theoretical characteristics
mb89530 series 49 (continued) 004 h 003 h 002 h 001 h av ss avr 3ff h 3fe h 3fd h 3fc h avr 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss avr v nt (1 lsb n + v ot ) v (n + 1) t v nt n + 1 h n h n ? 1 h n ? 2 h av ss avr zero transition error analog input full-scale transition error digital output digital output linear error analog input differential linear error analog input digital output digital output ? 1 differential linear error in digital output n v ( n + 1 ) t ? v nt 1 lsb actual conversion characteristics actual conversion characteristics v ot (actual measurement value) actual conversion characteristics v fst ( actual measurement value ) actual conversion characteristics actual conversion characteristics v ot ( actual measurement value ) v fst (actual measure- ment value) theoretical characteristics actual conversion characteristics actual conversion characteristics theoretical characteristics actual conversion characteristics analog input linear error in digital output n v nt ? {1 lsb n + v ot } 1 lsb theoretical characteristics = = analog input
mb89530 series 50 (5) precautionary information input impedance of analog input pins the a/d converter has a sample & hold circuit as show n below, which uses a sample-and-hold capacitor to obtain the voltage at the analog input pin for 8 instruction cycles following the start of a/d conversion. for this reason if the external circuits providing the analog input signal have high output impedance, the analog input voltage may not stabilize within the analog input samp ling time. it is therefore recommended that the output impedance of external circuits be reduced to 10 k ? or less. about error the smaller the absolute value |avr - avss| is, the greater the relative error becomes. mb89537/537c/538/538 c/f538l analog inpu t equivalent circuit c = 49 pf r = 7.1 k ? if analog input impedance is 10 k ? or more, the use of a capacitor of approximately 0.1 f is recom- mended. analog input pin sample-and-hold circuit compara- tor closes 8 instruction cycles after the start of a/d conversion analog channel selector mb89p538 and mb89pv530 anal og input equivalent circuit c = 64 pf r = 3 k ? if analog input impedance is 10 k ? or more, the use of a capacitor of approximately 0.1 f is recom- mended. analog input pin sample-and-hold circuit compar- ator closes 8 instruction cycles after the start of a/d conversion analog channel selector
mb89530 series 51 6. flash memory flash memory programming/erase characteristics * : excludes internal programming time before erase. parameter conditions value unit remarks min typ max sector erase time per 1 sector, constant value inde- pendent with sector ca- pacitance t a = + 25 c, v cc = 3.3 v ? 115s* program- ming time per 1 byte ? 8 3600 s chip erase time ? 5 ? s* program/erase cycle ? 10000 ?? cycle
mb89530 series 52 example characteristics (1) power supply current (external clock) (2) ?h? level input voltage/ ?l ? level input voltage (cmos input) (3) ?h? level input voltage / ?l? le vel input voltage (hysteresis input) mb89538 i cc1 vs. v cc 0 1 2 3 4 5 6 7 134 25 v cc (v) i cc1 (ma) (t a = + 25 ?c) 12.5 mhz 1 mhz 2 mhz 5 mhz 8 mhz 10 mhz mb89538 i ccs1 vs. v cc 0 0.5 1 1.5 2 2.5 134 25 v cc (v) i ccs1 (ma) (t a = + 25 ?c) 12.5 mhz 1 mhz 2 mhz 5 mhz 8 mhz 10 mhz mb89538 v in vs. v cc 0 1 2 3 4 2 2.5 3 3.5 4 v cc (v) v in (v) (t a = + 25 ?c) mb89538 v in vs. v cc 0 1 2 3 2 2.5 3 3.5 4 v cc (v) v in (v) (t a = + 25 ?c) v ih v il
mb89530 series 53 (4) a/d converter characteristic example -2.5 0 1.5 2 2.5 0 640 768 896 512 1024 (v cc = avr = 3 v, f ch = 10 mhz) -1.5 -2 -1 -0.5 3 128 256 384 -3 1 0.5 0 1.5 2 0 640 768 896 512 1024 (v cc = avr = 3 v, f ch = 10 mhz) -1.5 -2 -1 -0.5 2.5 128 256 384 -2.5 1 0.5 -3 0 2 3 0 640 768 896 512 1024 (v cc = avr = 3 v, f ch = 10 mhz) -2 -1 4 128 256 384 -4 1 mb89538 linearity error error (lsb) conversion characteristic mb89538 differential linearity error error (lsb) conversion characteristic mb89538 total error error (lsb) conversion characteristic
mb89530 series 54 mask options * : f ch : main clock frequency no part number mb89537 mb89537c mb89538 mb89538c mb89f538l-101 mb89f538l-201 mb89p538-101 mb89p538-201 mb89pv530-101 mb89pv530-201 method of specification specify at time of mask order setting not possible setting not possible setting not possible 1 main clock select oscillator stabilization wait period (f ch * = 10 mhz) approx.2 14 /f ch * (approx.1.6 ms) approx.2 17 /f ch * (approx.13.1 ms) approx.2 18 /f ch * (approx.26.2 ms) selection available 2 18 /f ch * (approx. 26.2 ms) 2 18 /f ch * (approx. 26.2 ms) 2 18 /f ch * (approx. 26.2 ms) 2 clock mode selection ? 2-system clock mode ? 1-system clock mode selection available ? 101 : 1-system clock mode ? 201 : 2-system clock mode
mb89530 series 55 ordering information part number package remarks mb89537p mb89537cp mb89538p mb89538cp mb89f538l-101p mb89f538l-201p mb89p538-101p mb89p538-201p 64-pin plastic sh-dip dip-64p-m01 mb89537p and mb89538p do not have i 2 c functions. mb89537pf mb89537cpf mb89538pf mb89538cpf mb89f538l-101pf mb89f538l-201pf mb89p538-101pf mb89p538-201pf 64-pin plastic qfp fpt-64p-m06 mb89537pf and mb89538pf do not have i 2 c functions. mb89537pfm mb89537cpfm mb89538pfm mb89538cpfm mb89f538l-101pfm mb89f538l-201pfm MB89P538-101PFM mb89p538-201pfm 64-pin plastic lqfp fpt-64p-m09 mb89537pfm and mb89538pfm do not have i 2 c functions. mb89537pfv mb89537cpfv mb89538pfv mb89538cpfv 64-pin plastic lqfp fpt-64p-m03 mb89537pfv and mb89538pfv do not have i 2 c functions. mb89537pv4 mb89537cpv4 mb89538pv4 mb89538cpv4 mb89f538l-101pv4 mb89f538l-201pv4 64-pin plastic bcc lcc-64p-m19 mb89537pv4 and mb89538pv4 do not have i 2 c functions. mb89pv530c-101 mb89pv530c-201 64-pin ceramic mdip mdp-64c-p02 mb89pv530cf-101 mb89pv530cf-201 64-pin ceramic mqfp mqp-64c-p01
mb89530 series 56 package dimensions please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html (continued) 64-pin pl as tic s h-dip le a d pitch 1.77 8 mm(70mil) p a ck a ge width p a ck a ge length 17 5 8 mm s e a ling method pl as tic mold mo u nting height 5.65 mm max 64-pin pl as tic s h-dip (dip-64p-m01) (dip-64p-m01) c 2001 fujit s u limited d64001 s -c-4-5 5 8 .00 +0.22 ?0.55 +.009 ?.022 2.2 83 17.000.25 (.669.010) 3 . 3 0 +0.20 ?0. 3 0 .1 3 0 ?.012 +.00 8 +.02 8 ?.00 8 .195 ?0.20 +0.70 4.95 +.016 ?.00 8 .054 3 ?0.20 +0.40 1. 3 7 8 1.77 8 (.0700) 0.470.10 (.019.004) 1.00 +0.50 ?0 .0 3 9 ?.0 +.020 +.020 ?.007 .02 8 ?0.19 +0.50 0.70 19.05(.750) (.011.004) 0.270.10 0~15 index-2 index-1 m 0.25(.010) note: pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s .
mb89530 series 57 please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html (continued) 64-pin pl as tic lqfp le a d pitch 0.50 mm p a ck a ge width p a ck a ge length 10.0 10.0 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm max weight 0. 3 2g code (reference) p-lfqfp64-10 10-0.50 64-pin pl as tic lqfp (fpt-64p-m0 3 ) (fpt-64p-m0 3 ) lead no. det a il s of "a" p a rt 0.25(.010) ( s t a nd off) (.004.004) 0.100.10 (.024.006) 0.600.15 (.020.00 8 ) 0.500.20 1.50 +0.20 ?0.10 +.00 8 ?.004 .059 0 ? ~ 8 ? "a" 0.0 8 (.00 3 ) (.006.002) 0.1450.055 0.0 8 (.00 3 ) m (.00 8 .002) 0.200.05 0.50(.020) 12.000.20(.472.00 8 ) s q 10.000.10(. 3 94.004) s q index 49 64 33 4 8 17 3 2 16 1 200 3 fujit s u limited f64009 s -c-5- 8 c (mo u nting height) * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 ) pin s width do not incl u de tie ba r c u tting rem a inder.
mb89530 series 58 please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html (continued) 64-pin pl as tic qfp le a d pitch 1.00 mm p a ck a ge width p a ck a ge length 14 20 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 3 . 3 5 mm max code (reference) p-qfp64-14 20-1.00 64-pin pl as tic qfp (fpt-64p-m06) (fpt-64p-m06) c 200 3 fujit s u limited f6401 3s -c-5-5 0.20(.00 8 ) m 1 8 .700.40 (.7 3 6.016) 14.000.20 (.551.00 8 ) 1.00(.0 3 9) index 0.10(.004) 119 20 3 2 52 64 33 51 20.000.20(.7 8 7.00 8 ) 24.700.40(.972.016) 0.420.0 8 (.017.00 3 ) 0.170.06 (.007.002) 0~ 8 ? 1.200.20 (.047.00 8 ) 3 .00 +0. 3 5 ?0.20 (mo u nting height) .11 8 +.014 ?.00 8 0.25 +0.15 ?0.20 .010 +.006 ?.00 8 ( s t a nd off) det a il s of "a" p a rt "a" 0.10(.004) * * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 )pin s width do not incl u de tie ba r c u tting rem a inder.
mb89530 series 59 please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html (continued) 64-pin pl as tic lqfp le a d pitch 0.65 mm p a ck a ge width p a ck a ge length 12 12 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm max code (reference) p-lqfp64-12 12-0.65 64-pin pl as tic lqfp (fpt-64p-m09) (fpt-64p-m09) c 200 3 fujit s u limited f6401 8s -c- 3 -5 0.65(.026) 0.10(.004) 116 17 3 2 49 64 33 4 8 12.000.10(.472.004) s q 14.000.20(.551.00 8 ) s q index 0. 3 20.05 (.01 3 .002) m 0.1 3 (.005) 0.1450.055 (.0057.0022) "a" .059 ?.004 +.00 8 ?0.10 +0.20 1.50 0~ 8 ? 0.25(.010) (mo u nting height) 0.500.20 (.020.00 8 ) 0.600.15 (.024.006) 0.100.10 (.004.004) det a il s of "a" p a rt ( s t a nd off) 0.10(.004) * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 ) pin s width do not incl u de tie ba r c u tting rem a inder.
mb89530 series 60 please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html (continued) 64-pin cer a mic mdip le a d pitch 1.77 8 mm (70mil) row s p a cing 15.24mm (750mil) mother b o a rd m a teri a l cer a mic mo u nted p a cking m a teri a l pl as tic 64-pin cer a mic mdip (mdp-64c-p02) (mdp-64c-p02) +0.1 3 ?0.0 8 +.005 ?.00 3 index area 0~9 (.750.012) 19.050. 3 0 0.46 .01 8 (2.240.025) (.010.002) 0.250.05 (.050.010) 1.270.25 (.1 3 5.015) 3 .4 3 0. 38 55.12(2.170)ref (.0 3 5.005) 0.900.1 3 (.070.010) 1.77 8 0.25 10.16(.400)max 33 .02(1. 3 00)ref (.100.010) 2.540.25 (.7 38 .012) 1 8 .750. 3 0 typ 15.24(.600) 56.900.64 1994 fujit s u limited m64002 s c-1-4 c dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s .
mb89530 series 61 please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html (continued) 64-pin cer a mic mqfp le a d pitch 1.00 mm le a d s h a pe s tr a ight mother b o a rd m a teri a l cer a mic mo u nted p a ck a ge m a teri a l pl as tic 64-pin cer a mic mqfp (mqp-64c-p01) (mqp-64c-p01) c 1994 fujit s u limited m64004 s c-1- 3 15.5 8 0.20 (.61 3 .00 8 ) 16. 3 00. 33 (.642.01 3 ) 1 8 .70(.7 3 6)typ index area 0. 3 0(.012) typ 1.270.1 3 (.050.005) 22. 3 00. 33 (. 8 7 8 .01 3 ) 24.70(.972) typ 10.16(.400) typ 12.02(.47 3 ) typ 14.22(.560) typ 1 8 .120.20 (.71 3 .00 8 ) 1.270.1 3 (.050.005) 0. 3 0(.012)typ 7.62(. 3 00)typ 9.4 8 (. 3 7 3 )typ 11.6 8 (.460)typ 0.50(.020)typ 0.150.05 (.006.002) 10. 8 2(.426) max 0.400.10 (.016.004) .047 ?.00 8 +.016 ?0.20 +0.40 1.20 0.400.10 (.016.004) 1.000.25 (.0 3 9.010) 1 8 .00(.709) typ 1.000.25 (.0 3 9.010) 12.00(.472)typ .047 ?.00 8 +.016 ?0.20 +0.40 1.20 dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s .
mb89530 series 62 (continued) please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html 64-pin pl as tic bcc le a d pitch 0.50 mm p a ck a ge width p a ck a ge length 9.00 mm 9.00 mm s e a ling method pl as tic mold mo u nting height 0. 8 0 mm max weight 0.10g 64-pin pl as tic bcc (lcc-64p-m19) (lcc-64p-m19) c 2002 fujit s u limited c64019 s -c-1-1 1 17 49 33 0.500.10 (.020.004) 0.50(.020) typ 8 .10(. 3 19) typ 8 .20(. 3 2 3 ) typ "c" "b" "a" 7.00(.276)ref 7.00(.276) ref 0.500.10 (.020.004) 0.50(.020) typ 8 .10(. 3 19)typ 8 .20(. 3 2 3 )typ (0. 8 0(.0 3 1)max) 0.0750.025 (.00 3 .001) 17 33 49 1 9.000.10(. 3 54.004) ( s t a nd off) 9.000.10 (. 3 54.004) 0.05(.002) 0.550.06 (.022.002) 0.550.06 (.022.002) det a il s of "b" p a rt c0.2(.00 8 ) 0. 3 00.06 (.012.002) 0.700.06 (.02 8 .002) det a il s of "a" p a rt det a il s of "c" p a rt 0.550.06 (.022.002) 0.550.06 (.022.002) (mo u nt height) index area 8 .25(. 3 25)ref 8 .25(. 3 25) ref "a" (.024.002) 0.600.06 0. 3 00.06 (.012.002) 0.14(.006)min. dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s .
mb89530 series 63 main changes in this edition (continued) page section change results 5 model differences and selection considerations for part number mb89537/ 537c and mb89538/538c with lcc-64p-m19 package, changes are as follows : x o deleted the row lcc-64p-m16 deleted the table footnote?* : only for es? 10 pin assignments deleted the ?(lcc-64p-m16) * 4 ? ?*4 : only for es? 13 pin descriptions changed as follows in the section mb89p538, the pin name c : v ss is fixed. if ?available? is selected for the stepdown circuit stabilization time, v cc is fixed. if ?unavailable? is selected for the step-down circuit stabilization time, v ss is fixed. changed the table footnote : *6 : lcc-64p-m19/m16 * 6 : lcc-64p-m19 18 handling devices 9. details on handling c terminal of mb89530 series changed in the figure : (2 19 /fch) (2 19 /f ch ) + (2 18 /f ch ) 20 programming an d erasing flash memory on the mb89f538 6. rom programmer adaptor and recommended rom programmers changed in the recommended programmer manufacturer and model : ando electric co. ltd. flash support group, inc. 21 one-time writing specifications with prom and eprom microcontrollers ? rom writer adapters deleted the row lcc-64p-m16 deleted the table footnote ?* 2 : only for es? 24 block diagram changed in the diagram : x1 x1 ? mod2* 1 , c, v cc mod2* 1 , v cc 34 to 36 electrical characteristics 2. recommended operating conditions ? operating voltage vs. operating frequency (mb89537/mb89538/mb89537c/mb89538c) ? operating voltage vs. operating frequency (mb89f538l) ? operating voltage vs. operating frequency (mb89p538/mb89pv530) changed in the figure : (at instruction cycle = 4/fc) (at instruction cycle = 4/f ch ) 40 electrical characteristics 4. ac characteristics (3) clock timing standards changed the input clock pulse width : p whh p whl 41 changed in the x0a, x1 a timing and application conditions : p wlh p whl added ?rd? in the clock application conditions
mb89530 series 64 (continued) the vertical lines marked in the left side of the p age show the changes. page section change results 53 example characteristics (4) a/d converter characteristic example changed in the figure : fc = 10 mhz f ch = 10 mhz 55 ordering information added the follo wing part numbers and remarks in the row of lcc-64p-m19 : part number : mb89537pv4, mb89537cpv4, mb89538pv4, mb89538cpv4 remarks : mb89537pv4 and mb89538pv4 do not have i 2 c functions. deleted the row lcc-64p-m16 deleted the table footnote ?* : only for es? 62 package dimensions deleted the 64-pin, plastic bcc (lcc-64p-m16)
mb89530 series f0704 the information for microcontroller suppor ts is shown in the following homepage. http://www.fujitsu.com/global/s ervices/microelectronics/produ ct/micom/support/index.html fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited business promotion dept.

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